Viewpoint: Keep design innovation alive
By Rob Irwin, Altium Limited
edadesignline.com (June 17, 2009)
There's perhaps a weary inevitability attached to the start of any new electronics design project that's been accepted for too long: after deciding what devices to target, you need to spend significant time 'tooling up'.
This generally involves finding and sourcing development boards and software that will allow you to 'play' with the devices on your short list.
Most designers accept this as necessity because that's the way it's always been done.
Time to take a step back, look at what's happening around you, and see that this is, frankly, clumsy, unresponsive, stifling of innovation and equally stifling of enjoyment!
Take for instance the notion that the first thing to do is choose the major devices around which you will base the design. Routine and precedent has it that you select the processor, the major peripheral chips and, increasingly, the FPGA.
It's logical, you argue, to set these
edadesignline.com (June 17, 2009)
There's perhaps a weary inevitability attached to the start of any new electronics design project that's been accepted for too long: after deciding what devices to target, you need to spend significant time 'tooling up'.
This generally involves finding and sourcing development boards and software that will allow you to 'play' with the devices on your short list.
Most designers accept this as necessity because that's the way it's always been done.
Time to take a step back, look at what's happening around you, and see that this is, frankly, clumsy, unresponsive, stifling of innovation and equally stifling of enjoyment!
Take for instance the notion that the first thing to do is choose the major devices around which you will base the design. Routine and precedent has it that you select the processor, the major peripheral chips and, increasingly, the FPGA.
It's logical, you argue, to set these
To read the full article, click here
Related Semiconductor IP
- Secure Boot Loader
- Memory Subsystem
- 4/8-bit mixed-precision NPU IP
- Compiler-centric single-core LPU
- SMC 2nm 1V8 ESD Power Clamp – Low Leakage
Related Articles
- Ultra Ethernet's Design Principles and Architectural Innovations
- Engineers caught between innovation and cost-cutting
- Speakers call for innovation in verification
- Innovation to drive chip performance curve
Latest Articles
- Versat-AI: An ONNX-to-SoC Compiler for Model-Agnostic CGRA Edge Inference
- HyNoC: A Hybrid Circuit-Switch/Wormhole Network-on-Chip for Distributed VLIW Computing on FPGA
- Hybrid ASIC-FPAA Fabric for Performance Security Trade-off
- A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection