Are design and test conflicting or symbiotic?
Arif Samad, Synopsys
EEtimes (10/20/2010 2:32 AM EDT)
These days, IC design engineers have more functionality to implement in their designs than ever before, even though design schedules are shrinking. Although design-for-test (DFT) is absolutely necessary to enable thorough and cost-effective manufacturing test, it potentially makes the overall design process even more challenging.
The paradigm of the designer “throwing the design over the wall” to the test engineer was viable in the days when DFT was limited to adding scan chains to a design, and timing delays of the signal propagation across gates were relatively greater than across the interconnects. But the old paradigm no longer applies in an era where advanced DFT methodologies are necessary to limit test cost, interconnect delays are dominant and power consumption critical.
To read the full article, click here
Related Semiconductor IP
- Verification IP for C-PHY
- Band-Gap Voltage Reference with dual 2µA Current Source - X-FAB XT018
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
Related Articles
- SoCs lend momentum to design-for-test solutions
- SOC: Submicron Issues -> Physics dictates priority: design-for-test
- DFT – IP Reuse & SoC
- DFT for SoC : The Economic Myths
Latest Articles
- SCENIC: Stream Computation-Enhanced SmartNIC
- Agentic AI-based Coverage Closure for Formal Verification
- Microarchitectural Co-Optimization for Sustained Throughput of RISC-V Multi-Lane Chaining Vector Processors
- RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
- Emulation-based System-on-Chip Security Verification: Challenges and Opportunities