Applying Constrained-Random Verification to Microprocessors
By Jason C. Chen, Synopsys Inc.
December 10, 2007 -- edadesignline.com
Constrained-random verification (CRV) offers a highly effective way to deal with the challenges of microprocessor verification. These verification challenges are overwhelming for many reasons: complex instruction sets, multiple pipeline stages, in-order or out-of-order execution strategies, instruction parallelism, fixed- and floating-point scalar/vector operations, and other features that create a seemly never-ending list of corner cases to exercise. The time required to create traditional directed tests has become unreasonable.
Language features such as the SystemVerilog random sequence generator allow you to create instruction sequences randomly to improve stimulus quality based on a structured set of rules and scenarios. Such random-sequence generation schemes are procedural, however, and do not take full advantage of object-based randomization using constraints.
This article proposes an object-oriented solution for processor verification challenges. The solution covers both a top-down stimulus planning process and a bottom-up implementation solution using SystemVerilog and commercially available base classes (such as those in Synopsys's Verification Methodology Manual, VMM). The description that follows covers the most important parts of this solution and uses a processor supporting the MIPS-I instruction set as an example design under test (DUT).
December 10, 2007 -- edadesignline.com
Constrained-random verification (CRV) offers a highly effective way to deal with the challenges of microprocessor verification. These verification challenges are overwhelming for many reasons: complex instruction sets, multiple pipeline stages, in-order or out-of-order execution strategies, instruction parallelism, fixed- and floating-point scalar/vector operations, and other features that create a seemly never-ending list of corner cases to exercise. The time required to create traditional directed tests has become unreasonable.
Language features such as the SystemVerilog random sequence generator allow you to create instruction sequences randomly to improve stimulus quality based on a structured set of rules and scenarios. Such random-sequence generation schemes are procedural, however, and do not take full advantage of object-based randomization using constraints.
This article proposes an object-oriented solution for processor verification challenges. The solution covers both a top-down stimulus planning process and a bottom-up implementation solution using SystemVerilog and commercially available base classes (such as those in Synopsys's Verification Methodology Manual, VMM). The description that follows covers the most important parts of this solution and uses a processor supporting the MIPS-I instruction set as an example design under test (DUT).
To read the full article, click here
Related Semiconductor IP
- nQrux® Root of Trust IP
- AXI to UCIe Bridge IP
- UCIe 2.x Controller IP
- SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP
- OpenTitan-based RISC-V Secure Element
Related Articles
- A Comparison of Assertion Based Formal Verification with Coverage driven Constrained Random Simulation, Experience on a Legacy IP
- Methodology Independent Exhaustive Constraint Solver for Random Verification and Regression Generation
- Strategies for verifying microprocessors
- Lockdown! Random Numbers Secure Network SoC Designs
Latest Articles
- A Secure dToF LiDAR SoC with Dual-Domain Fingerprinting and Event-Driven AFE Circuit Achieving Sensor-Level Attack Resilience
- ZTA-Q: an Open-source RISC-V Platform for Accurate Quantized CNN Inference
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM