Conquering behemoth designs

Andy Inness, Mentor Graphics
EETimes (6/11/2012 10:10 AM EDT)

If the IC design trends of the past 20 years serve as an example, we will likely be required to implement a trillion transistors or more on a chip in the next 10 years.  Even at 20nm, chip sizes touching billions of transistors present the age old, perpetually unanswered problem of how to most efficiently implement a design of staggering magnitude. Do you do it flat or hierarchical? Are your decisions based on the current tool capabilities or limitations? Is the design being implemented across geographies or locally? Is it a complex SoC or an ASIC? Do you have any 3rd party IPs or analog components? Is the market window three months or three years away? Do you have a fixed area or power budget that must be met?

Tools and methodologies for the physical implementation of these big designs—from synthesis through place and route, verification, and DFM—have typically used either a purely flat implementation, or a hierarchical implementation. Both the approaches have advantages and disadvantages, summarized in Table 1, but have worked reasonably well until the recent move to 20/14nm. At these advanced nodes, the current tools and methodologies seem to be running out of steam and the design community is looking for a solution that addresses the performance, complexity and time-to-market requirements while also handling large amounts of data.

In this article we discuss some strategies and tool requirements for physical implementation of such large and complex semiconductors. We make a case for a hybrid design methodology--a pseudo-flat flow that uses existing tools, technology, and design team infrastructure to enable better results in less time than the traditional flows.

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