Chiplet Strategy is Key to Addressing Compute Density Challenges
By Balaji Baktha, Ventana Micro Systems
EETimes (September 28, 2021)
Data center workloads are quickly evolving, demanding high compute density with varying mixes of compute, memory and IO capability. This is driving architectures that are moving away from a one-size-fits-all monolithic solution to disaggregated functions that can be independently scaled for specific applications.
It is imperative to adopt the latest process nodes to deliver the needed compute density. However, doing so with traditional monolithic SoCs presents an inherent disadvantage due to escalating costs and time to market challenges resulting in unfavorable economics. To address this dilemma, chiplet-based integration strategies are emerging where compute can benefit from the most advanced process nodes, while application-specific memory and IO integrations can reside on mature trailing process nodes.
To read the full article, click here
Related Semiconductor IP
- USB-C Power Delivery IP Core
- Configurable Multi-Channel DMA Controller
- Samsung Foundry 4nm 1V8 GPIO I3C
- Root-of-Trust IP - High-Assurance Security for Advanced and Regulated Applications
- Root-of-Trust IP - Enhanced-Assurance, Configurable Security for Scalable Semiconductor Designs
Related Articles
- Reconfiguring Design -> Reconfigurability: Designer's key strategy
- Clock domain modeling is essential in high density SoC design
- Addressing the new challenges of ASIC/SoC prototyping with FPGAs
- Addressing MIPI M-PHY connectivity challenges for more efficient testing
Latest Articles
- GSPIM: A Temporal-Locality-Aware 4D Gaussian Splatting Accelerator with Polymorphic PIM and Multi-Frame Rendering Dataflow
- Memory Admission and Result-Retention Sizing in an RV32IMC FPGA Soft Processor
- A Cross-Domain Matrix Engine for Signal Processing and Deep Neural Net Inference
- LLM Agent-Based Design of RISC-V CPUs with FPGA-in-the-Loop Evaluation
- Automated Multi-Line Bug Repair Using Model Checker Aided LLMs: A Case Study on RISC-V Processors