ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design

By Zhongkai Yu ¹, Chenyang Zhou ², Yichen Lin ¹, Hejia Zhang ¹, Haotian Ye ¹, Junxia Cui ¹, Zaifeng Pan ¹, Jishen Zhao ¹, Yufei Ding ^1
1 Department of Computer Science and Engineering, University of California San Diego, La Jolla, US
² Columbia University, New York, US. 

Abstract

While Large Language Models (LLMs) show significant potential in hardware engineering, current benchmarks suffer from saturation and limited task diversity, failing to reflect LLMs’ performance in real industrial workflows. To address this gap, we propose a comprehensive benchmark for AI-aided chip design that rigorously evaluates LLMs across three critical tasks: Verilog generation, debugging, and reference model generation. Our benchmark features 44 realistic modules with complex hierarchical struc tures, 89 systematic debugging cases, and 132 reference model samples across Python, SystemC, and CXXRTL. Evaluation results reveal substantial performance gaps, with state-of-the art Claude-4.5-opus achieving only 30.74% on Verilog generation and 13.33% on Python reference model generation, demonstrating significant challenges compared to existing saturated benchmarks where SOTA models achieve over 95% pass rates. Additionally, to help enhance LLMreference model generation, we provide an automated toolbox for high-quality training data generation, facilitating future research in this underexplored domain. Our code is available at https://github.com/zhongkaiyu/ChipBench.git.

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