Characterizing licensable core performance; Find out why comparing processor cores is tricky and learn what to look for.

[Editor's note: If you are unfamiliar with the concepts of chip fabrication, the article "Push performance and power beyond the data sheet" provides some useful background.]
Comparing licensable processor cores and quantifying their relative performance is challenging. Unlike processor chips, there are many different ways in which licensable cores can be configured, implemented, and fabricated, each of which yields a different combination of speed, area, and power consumption. Particularly for digital signal processing applications (which tend to push the limits on one or more of these metrics) it's essential to have reliable and accurate performance data.
To make apples-to-apples comparisons between cores you'll need to pin down a consistent set of assumptions. In this article, we'll discuss some of the factors to consider when assessing and comparing licensable cores for digital signal processing.
To read the full article, click here
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Articles
- Agile Analog's Approach to Analog IP Design and Quality --- Why "Silicon Proven" is NOT What You Think
- Find out what's really inside the iPod; Reuse of components is a good design practice for similar applications, including mobile handsets
- Performance analysis of 8-bit pipelined Asynchronous Processor core
- Why VAD and what solution to choose?
Latest Articles
- LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
- A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node
- Automated Estimation of MBIST Area and Test Time in Heterogeneous Memory IPs via Stacked Ensemble Framework
- VIPER: Architecture-Aware Performance Modeling for Processing-in-Memory Design-Space Exploration
- CTTE: An Open Dual-Protocol RISC-V Trace Encoder for N-Trace and E-Trace