Broadcast video infrastructure implementation using FPGAs
Tam Do, Senior Technical Marketing Manager, Broadcast/Consumer Applications Business Unit, Altera
Jun 07, 2006 (2:00 PM), CommsDesign
Introduction
The proliferation of high-definition television (HDTV) video content creation and the method of delivering these contents in a bandwidth-limited broadcast channel environment have driven new video compression standards and associated video image processing applications. Traditionally, only cable and satellite operators provided video delivery. Now telecommunication companies (telcos) are getting into this arena by using the latest video coder/decoders (CODECs) and video-processing technology to transmit digital video to the consumer via Internet protocol television (IPTV).
To read the full article, click here
Related Semiconductor IP
- Band-Gap Voltage Reference with dual 2µA Current Source - X-FAB XT018
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
Related Articles
- Emerging H.264 standard supports broadcast video encoding
- Automated video algorithm implementation
- Polyphase Video Scaling in FPGAs
- How to implement a high-definition video design framework for FPGAs
Latest Articles
- SCENIC: Stream Computation-Enhanced SmartNIC
- Agentic AI-based Coverage Closure for Formal Verification
- Microarchitectural Co-Optimization for Sustained Throughput of RISC-V Multi-Lane Chaining Vector Processors
- RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
- Emulation-based System-on-Chip Security Verification: Challenges and Opportunities