Boundary scan and JTAG emulation combine for advanced structural test and diagnostics
By Heiko Ehrenberg & Thomas Wenzel (Goepel Electronics Ltd.)
EE Times Europe (11/10/09, 04:02:00 AM EST)
While continuously improving IC and SOC technologies, higher clock rates, and more powerful processors are music to the design engineers' ears, the headaches of test engineers are getting worse and worse.
The ever decreasing test access was the worrying factor in the past, but a new problem arose in recent years with the dramatically increasing speed of the signal transmission.
The resulting failure phenomena and test access limitations have an inevitable impact on the efficiency and practicality of test strategies.
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