Best design practices for DFT
Gunjot Kaur , Sidhant Goel & Mayank Parasrampuria (Freescale)
EDN (October 14, 2015)
SoC sub-components (IPs) generally come from various sources – internal and external – and with that it has become necessary that designers ensure the RTL is testable. If the RTL has testability issues, test coverage goals can’t be met and the RTL needs to be modified, which means several iterations of synthesis, verification, and Automatic Test Pattern Generation (ATPG).
Here we will discuss the basic design practices to ensure proper testability.
To read the full article, click here
Related Semiconductor IP
- MIL-STD-1553 Controller IP
- UFS 5.x Device IP
- UCIe 3.x Controller IP
- Ethernet 800G PCS IP
- CHI to UCIe Bridge IP
Related Articles
- SoC designers describe their 'best practices'
- Best Practices for a Reusable Verification Environment
- MBIST verification: Best practices & challenges
- Generative AI for Analog Integrated Circuit Design: Methodologies and Applications
Latest Articles
- CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research
- Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs