Analysis: ARC's Configurable Video Subsystems
August 29, 2007 -- dspdesignline.com
Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1. (The middle of the family range is filled out by the AV 404V, AV 406V, and AV 407V). The AV 40xV family subsystems are intended for compression-centric applications such as camera phones, portable media players, DVB-H and DVD players.
To read the full article, click here
Related Semiconductor IP
- Ultra Ethernet MAC & PCS 100G/200G/400G/800G
- Ethernet PCS 100G/200G/400G/800G/1.6T
- Ethernet MAC 100G/200G/400G/800G/1.6T
- Junction Over-Temperature Detector with Linear Centigrade-to-Voltage Output - X-FAB XT018
- Performance P570 Gen 3
Related Articles
- A Methodology for Performance Analysis of Network-on-Chip Architectures for Video SoC
- A Performance Architecture Exploration and Analysis Platform for Memory Sub-systems
- Configurable Processors for Video Processing SOCs
- Creating multi-standard, multi-resolution video engines using configurable processors
Latest Articles
- Closer in the Gap: Towards Portable Performance on RISC-V Vector Processors
- TTP: A Hardware-Efficient Design for Precise Prefetching in Ray Tracing
- Heterogeneous SoC Integrating an Open-Source Recurrent SNN Accelerator for Neuromorphic Edge Computing on FPGA
- A Reconfigurable Multiplier Architecture for Error-Resilient Applications in RISC-V Core
- ObfAx: Obfuscation and IP Piracy Detection in Approximate Circuits