Opportunities in Analog Verification

By Saranyan Vigraham, Qualcomm
edadesignline.com (October 28, 2008)

The wireless industry is continuously innovating and re-shaping the state-of-the-art techniques in analog and RF circuit design. The analog systems are getting increasingly challenging to design and even more to verify. The industry is seeing a bigger risk of functional failure in these systems or sub-systems as compared to the past decade. Functional failures can mean any of the following things and more -- Chip not powering on, inverted logic due to improper connectivity, clocks not propagating all the way to a core block, registers not getting updated, wrong modes of operation, incorrect performance in some of the gain modes in an amplifier, etc.

Normally speaking, these things should never happen and a chip must be verified for all these factors before tapeout. Usually, the circuit designers do this in the analog domain. However, these days an increasing demand for specialized verification engineers has been noted in the industry. The reasons primarily being the increasing complexity of block interactions that will cause "accidental" goof-up in connections or logic, and an alternate mindset and skills needed to do the job.

Verification engineers have to be capable of thinking beyond a particular block and formulate their verification strategies in the context of the complete system. Also, verification engineers must be able to abstract a system to the simplest form needed to conduct the tests. Programming skills, scripting and little bit of design skills go a great deal in forming a strong verification engineer. There are different aspects of system verification -- performance and functional.

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