Analog IP verification guidelines

Stefano Pietri, Freescale Semiconductor
EDN (November 18, 2015)

Most bugs in analog circuits can be avoided by defining the optimal design margins, following strict verification procedures, and adhering to commonsense guidelines. Finding the right trade-off is a moving target that changes with technology and market priorities. However, the increasing mask costs of advanced nodes make thorough verification a greater necessity than ever. In this short paper we describe the steps that are followed in the Automotive Microcontroller Division of Freescale Semiconductor in order to fully verify analog IPs.

1. Simulation environment

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KISS principle

• Keep It Small and Simple. Verification plans (like designs) have a better chance to work when simple.
• Include all the necessary simulations sufficient to fully verify the IP, without falling into overly complicated or overly simplistic cases.
• A good verification deliverable is a document (verification plan) that has links to each circuit test bench required to fully simulate the IP and a description for each link that explains what the simulation is accomplishing or trying to verify.

Pick your verification sign off specifications carefully

• Each line/specification in the Data Sheet (DS) should be addressed in at least a simulation test bench.
• At an early design stage when the DS may not be not available, a preliminary architectural document with tentative specifications can be used instead.
• Each electrical specification will meet production limits with a CPK value with a PASS/FAIL check (For 6 sigma design practices CPK ≥ 1.67).
• Do not apply PASS/FAIL for specs that are "nice to have”. It will avoid over-design.
• If it is not possible to calculate a CPK for a spec directly (e.g., ADC ENOB), the CPK shall be derived from all contributing parameters.
• Electrical specifications in the DS must be tagged appropriately as Simulation/Characterization/Test in the verification document and match the DS.

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