Analog switches in D-PHY MIPI dual camera/dual display applications (Part 2 of 2)
Graham LS Connolly, Principal Engineer, and Tony Lee, Applications Engineer, Fairchild Semiconductor Corp.
3/16/2011 1:08 PM EDT
(Part 1 looked at the nature of the problem, as well as the requirements of D-PHY MIPI® dual camera/dual display applications, click here to read it.)
What is the solution?
The solution is to add an analog switch.
When inserting an analog switch, the key influencing factor is still the incident wave response, as the switch can be seen as a discontinuity. The switch RC characteristics have to be optimized to facilitate good âeyeâ performance by minimizing reflections and edge rate degradation. Initially, the extra CON/COFF of the switch may be viewed as a detriment to the system performance, but in reality, removing the discontinuity reflections outweighs the extra capacitance and series resistance incurred by inserting the analog switch. The MIPI specifications use a 0.3 UI (unit interval) for the criteria of Interoperability, so the faster you want to run your system, the more critical the switch CON/COFF characteristics becomes, since that is the parameter that will impact the edge rate and, therefore, the 0.3 UI criteria.
To read the full article, click here
Related Semiconductor IP
- Chiplet Die-to-Die Interconnect IP Solution
- High speed MACsec Engine 100G/200G/400G/800G/1.6T
- Temperature/Voltage sensors
- AMBA Bus Host to eSPI Controller/Target
- AMBA Bus Host to eSPI Controller
Related Articles
- Analog switches in D-PHY MIPI dual camera/dual display applications (Part 1 of 2)
- All you need to know about MIPI D-PHY RX
- A design of High Efficiency Combo-Type Architecture of MIPI D-PHY and C-PHY
- Demystifying MIPI C-PHY / DPHY Subsystem
Latest Articles
- ZK-Flex: A Flexible and Scalable Framework for Accelerating Zero-Knowledge Proofs
- ITP-STDP: An Intrinsic-Timing Power-of-Two Learning Engine for On-Chip SNN Training
- OpenEye: A Scalable Open-Source Hardware Accelerator for DNNs
- CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees
- CXL-ClusterSim: Modeling CXL-based Disaggregated Memory Cluster for Pooling and Sharing using gem5 and SST