All about FPGAs
By Bob Zeidman
This article examines field-programmable gate arrays (FPGAs) and their underlying architectures and technologies. We will also examine current and up-and-coming software tools that are designed to allow you to squeeze more functionality into these chips in less time, running at faster speeds, and using less power.
Introduction
The first section of this article deals with the internal architecture and characteristics of typical FPGA devices, allowing you to decide which particular device is right for your design. The next section examines new FPGA architectures being offered by various vendors. The final section looks at some new software tools to help you with your designs.
The basics of FPGAs
Field-programmable gate arrays (FPGAs) are so-called because they are structured very much like the now-obsolete "gate array" form of application specific integrated circuit (ASIC). In fact, FPGAs essentially killed the gate array ASIC business. In the not-so-distant past, FPGAs were marketed for primarily two uses: (a) for prototyping ASICs and (b) for use in systems to achieve time-to-market knowing that they would be replaced with an ASIC implementation at the earliest opportunity.
With regard to this latter point, FPGAs can be programmed on your desk top in minutes while ASICs require weeks to fabricate a new design. As FPGA speeds increased, power consumption decreased, and prices decreased, FPGAs began shipping in products without any intention of replacing them with equivalent ASICs. Of course FPGAs are still good at prototyping ASICs and they are still used that way.
This article examines field-programmable gate arrays (FPGAs) and their underlying architectures and technologies. We will also examine current and up-and-coming software tools that are designed to allow you to squeeze more functionality into these chips in less time, running at faster speeds, and using less power.
Introduction
The first section of this article deals with the internal architecture and characteristics of typical FPGA devices, allowing you to decide which particular device is right for your design. The next section examines new FPGA architectures being offered by various vendors. The final section looks at some new software tools to help you with your designs.
The basics of FPGAs
Field-programmable gate arrays (FPGAs) are so-called because they are structured very much like the now-obsolete "gate array" form of application specific integrated circuit (ASIC). In fact, FPGAs essentially killed the gate array ASIC business. In the not-so-distant past, FPGAs were marketed for primarily two uses: (a) for prototyping ASICs and (b) for use in systems to achieve time-to-market knowing that they would be replaced with an ASIC implementation at the earliest opportunity.
With regard to this latter point, FPGAs can be programmed on your desk top in minutes while ASICs require weeks to fabricate a new design. As FPGA speeds increased, power consumption decreased, and prices decreased, FPGAs began shipping in products without any intention of replacing them with equivalent ASICs. Of course FPGAs are still good at prototyping ASICs and they are still used that way.
To read the full article, click here
Related Semiconductor IP
- nQrux® Root of Trust IP
- AXI to UCIe Bridge IP
- UCIe 2.x Controller IP
- SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP
- OpenTitan-based RISC-V Secure Element
Related Articles
- All you need to know about MIPI D-PHY RX
- System-on-chip (SoC) design is all about IP management
- How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
- Stellamar's all-digital, fully-synthesizable, analog-to-digital converters for Microsemi FPGAs
Latest Articles
- A Secure dToF LiDAR SoC with Dual-Domain Fingerprinting and Event-Driven AFE Circuit Achieving Sensor-Level Attack Resilience
- ZTA-Q: an Open-source RISC-V Platform for Accurate Quantized CNN Inference
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM