How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
Allan Chin and Luciano Zoso, Stellamar
EETimes (1/18/2011 3:01 PM EST)
When we engineers look at the complexity of system design these days, we are challenged with cramming more functions into a smaller space, while consuming less power, and doing all of this in much shorter design cycles.
Efficient and effective analog design has always been a significant roadblock to hitting our deadlines; generally speaking, digital design and verification is much easier. This has certainly been true in our experience, which has involved spending the last 30 years learning the “art” of mixed-signal design.
Unfortunately, the ability to overcome the size and performance constraints of analog blocks is directly proportional to the mixed-signal engineer’s experience. Learning this art can take a lifetime. The time investment not only strains design cycles, but also hurts creativity, and it can be an impediment to cultivating a young, robust labor pool. The vast number of new graduates going into digital design as opposed to analog design is evidence of this. As a result, not much has truly been done to improve the underlying fabric of analog architecture and address inherent problems over the last 20 years.
To read the full article, click here
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Articles
- Stellamar's all-digital, fully-synthesizable, analog-to-digital converters for Microsemi FPGAs
- Modeling high-speed analog-to-digital converters
- Understanding Interface Analog-to-Digital Converters (ADCs) with DataStorm DAQ FPGA
- LVDS ups A/D converter data rates
Latest Articles
- LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
- A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node
- Automated Estimation of MBIST Area and Test Time in Heterogeneous Memory IPs via Stacked Ensemble Framework
- VIPER: Architecture-Aware Performance Modeling for Processing-in-Memory Design-Space Exploration
- CTTE: An Open Dual-Protocol RISC-V Trace Encoder for N-Trace and E-Trace