Agile Design for Hardware, Part I
David Patterson and Borivoje Nikolic, UC Berkeley
7/27/2015 07:00 AM EDT
In the first of a three-part series, two Berkeley professors suggest its time to apply Agile design techniques to hardware.
Software used to be developed as a sequence of distinct phases, each of which can take six or more months:
- Requirements analysis and specification
- Architectural design
- Implementation and integration
- Verification and test
- Operation and maintenance
This process is the called the Waterfall development model, since it flows from the top down to completion. Waterfall relies on extensive documentation, planning, and using PERT and Gantt charts to try to make the schedule match the budget.
So many software projects were late, over budget, or abandoned that it led to a revolution in software development, demarcated by the Agile Manifesto in 2001. Agile development embraces change as a fact of life; small teams continuously refine a working but incomplete prototype until the customer is happy with the result. What to do in the next iteration depends on the evaluation of the current one, as opposed to some master plan established at the beginning of the project. Thus, the elaborate planning and documentation of the Waterfall process is moot.
To read the full article, click here
Related Semiconductor IP
- NPU IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
- NVMe Validation Test Suite
- Hybrid Memory Cube Verification IP
Related Articles
- Agile Design for Hardware, Part II
- LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges
- David vs. Goliath: Can Small Models Win Big with Agentic AI in Hardware Design?
- ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
Latest Articles
- Terracotta: Enabling the Adoption of New DRAM Techniques via a Flexible DRAM Interface and Memory Controller
- A Framework for Accelerating Transformer Inference on RISC-V for Edge AI
- An Interleaved Parallel Dependent Quantization Hardware Architecture for H.266/VVC
- A Formal Security Analysis of CAN XL
- A Secure dToF LiDAR SoC with Dual-Domain Fingerprinting and Event-Driven AFE Circuit Achieving Sensor-Level Attack Resilience