A Resource-Efficient CNN-Based EEG Auditory Attention Decoding ASIC

By Qier Ma ¹, Richard George ¹, Stefan Scholze ¹, Jehn Constantin ², Tobias Reichenbach ², and Christian Mayr ^1
1 Department of Electrical Engineering and Information Technology, Institute of Circuits and Systems, Chair of Highly-Parallel VLSI Systems and Neuro-Microelectronics, Technische Universitat Dresden, Dresden, Germany
² Department of Artificial Intelligence in Biomedical Engineering (AIBE), Friedrich-Alexander-Universitat Erlangen–Nurnberg (FAU), Erlangen, Germany

Abstract

Following a target speaker in a noisy environment, commonly known as the cocktail party problem, remains particularly challenging for cochlear implant (CI) users. Recent studies have explored EEG-based auditory attention decoding (AAD) using neural networks to enhance hearing assistance. This paper presents a resource-efficient ASIC for real-time EEG-based auditory attention decoding by integrating a quantized CNN inference engine and a Pearson-correlation classifier. The proposed architecture employs streaming execution, on-chip buffering, and memory-efficient dataflow to reduce hardware cost while maintaining real-time performance.

The proposed ASIC has been fully implemented in GF22FDX 22-nm CMOS technology, occupying a total silicon area of 2.09 mm² (1264μm x 1654μm), with the CNN inference engine and streaming classification engine requiring only 0.076 mm². Operating at a core voltage of 0.55 V, the design achieves a power consumption of 0.4941 mW and an inference latency of 7.34 ms, providing an energy-efficient hardware platform for EEG-based auditory attention decoding in hearing-assistance applications.

Index Terms—Auditory Attention Decoding (AAD), EEG, ASIC, Low-Power Design, Cochlear Implant, CNN

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