Overcoming advanced SoC routing congestion with 2.5D system in packaging

Ayan Kumar Halder, Open Silicon Research
embedded.com (May 17, 2014)

Not very long ago, embedded systems were comprised of logic spread across multiple chips - for example, the CPU subsystem. Memory, the analog components, and so on, were each on their own IC. The advantage was that each chip could be independently designed at its appropriate process technology node (90nm, 130nm, etc.). However, the inter-connection between the chips consumed a significant amount of power, and there was high inter-chip communication latency as well as even higher risk of failure.

Then came the era of the SoC (System on Chip) where the various components (digital logic, analog logic, and memory sub-system) were placed on the same silicon chip. Thus the increased power consumption and latency issues observed with inter-chip communication in the previous design mechanism was ruled out. However, the disadvantage was that as the components were integrated in the same silicon, they had to be built at the same technology node (65nm, 40nm, 28nm, and so on).
While some logic, particularly the main processor, adds a greater value if it is designed at the latest technology node, the other components, such as memory, might not add that much value. However, the dilemma is that using traditional System-on-Chip methods, the chip designer has to choose the same process technology for all the logic. In addition to forcing the designer to create a less than silicon-efficient design, this also hindered reusability of some blocks, such as the CPU subsystem, as independent verified logic in the next system design.

The best of both worlds approach that the electronics industry has come up with to solve this dilemma is the System in Package (SiP) in a 2D package. Here multiple chips (DIE) are placed on a common substrate. Thus there can be a CPU-subsystem on one die, a memory subsystem on another, and analog logic on a third die.

Each DIE can be designed at its appropriate process technology node and later reused in later designs as Known Good DIEs (KDGs) which have been tested at wafer level. This reduces the time to market for the complete system, as KGDs can be reused with newer dies. The substrate carries a low power, low latency, high speed communication link between the DIEs.

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