2.5D ICs are more than a stepping stone to 3D ICs
Mike Santarini, Xilinx
EETimes (3/27/2012 2:04 PM EDT)
With Xilinx releasing last year the first commercially available 28nm, 2.5D Stacked Silicon Interconnect (SSI) device (the Virtex-7 2000T FPGA) followed by TSMC announcing full manufacturing and assembly support for 2.5D and 3D IC designs, the rest of the IC industry is starting to rev up efforts to make 2.5D and eventually 3D IC technology a mainstream reality.
2.5D has marked advantages of capacity, performance, system space and overall system power consumption over traditional single die implementations—3D promises to have even more. As a refresher, 2.5D, as implemented by Xilinx in the Virtex-7 2000T device, places several die (what Xilinx calls “slices”) side-by-side on a passive silicon interposer. Meanwhile, the industry envisions 3D ICs will stack two or more die (active-on-active) on top of each other and allow companies to achieve new levels of system integration by stacking the chips normally in a PCB in one or just a few devices (Figure 1).
The vision of a 3D IC is truly promising, but some industry watchers believe the 2.5D market is perhaps being too easily dismissed as a stepping stone to true 3D design. 2.5D has the distinct advantage of being already here today for some companies--and leveraging it takes only minor adjustments to current design flows and seemingly the manufacturing chain.
To read the full article, click here
Related Semiconductor IP
- MIL-STD-1553 Controller IP
- UFS 5.x Device IP
- UCIe 3.x Controller IP
- Ethernet 800G PCS IP
- CHI to UCIe Bridge IP
Related Articles
- Fully Depleted Silicon on Insulator devices
- Reconfiguring Design -> Adaptive computing makes efficient use of silicon
- Retargeting IP -> Silicon prototyping verifies IP functions
- Retargeting IP -> Design system compiles silicon straight from C code
Latest Articles
- CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research
- Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs