Tower Semiconductor Expands Foundry Solutions Portfolio with 0.16-Micron Optical Shrink
- New Process Improves Tower's Competitive Position
- 0.16-Micron Provides Lower Die Cost to Customers While Yields Higher Wafer Prices
"With our cost-effective 0.16-micron device solution, we are able to maintain the same design environment as 0.18-micron and make the required conversions while reducing the customer burden of designer-to-foundry interaction," said Doron Simon, president of Tower Semiconductor USA. "This translates to significant value for our existing customers while increasing our competitiveness in the marketplace."
The offering is tailored to customers who are looking to achieve cost reduction at the 0.18-micron technology node. Applications include industry standard CMOS logic and mixed-signal technologies. The 0.16-micron optical shrink solution is qualified and production ready. For customers looking to prototype their designs, the solution is available on the Tower Shuttle Program.
About Tower Semiconductor LTD.
Tower Semiconductor LTD. is a pure-play independent wafer foundry established in 1993. The company manufactures integrated circuits with geometries ranging from 1.0 to 0.13 micron; it also provides complementary technical services and design support. In addition to digital CMOS process technology, Tower offers advanced non-volatile memory solutions, mixed-signal and CMOS image-sensor technologies. To provide world-class customer service, the company maintains two manufacturing facilities: Fab 1 has process technologies from 1.0 to 0.35 micron and can produce up to 16,000 150mm wafers per month. Fab 2 features 0.18-micron and below process technologies, including foundry-standard technology. When complete, Fab 2 is expected to offer full production capacity of 33,000 200mm wafers per month. The Tower Web site is located at www.towersemi.com.
Safe Harbor
This press release includes forward-looking statements, which are subject to risks and uncertainties. Actual results may vary from those projected or implied by such forward-looking statements. Potential risks and uncertainties include, without limitation, risks and uncertainties associated with: (i) the completion of the equipment installation, technology transfer and ramp-up of production in Fab 2, (ii) having sufficient funds to complete the Fab 2 project, (iii) the cyclical nature of the semiconductor industry and the resulting periodic overcapacity, (iv) operating our facilities at satisfactory utilization rates, (v) the effect that our expected decrease in sales in the coming quarters will have on our ability to meet certain of the covenants stipulated in our amended facility agreement, which we currently forecast we will not meet in the next several quarters, (vi) our ability to capitalize on increases in demand for foundry services, (vii) meeting the conditions to receive Israeli government grants and tax benefits approved for Fab 2, which we currently forecast we may not meet, and obtaining the approval of the Israeli Investment Center to extend the five-year investment period under our Fab 2 approved enterprise program, (viii) attracting additional customers, (ix) not receiving orders from our wafer partners and technology providers, (x) failing to maintain and develop our technology processes and services, (xi) competing effectively, (xii) our large amount of debt, and (xiii) achieving acceptable device yields, product performance and delivery times. A more complete discussion of risks and uncertainties that may affect the accuracy of forward-looking statements included in this press release or which may otherwise affect our business is included under the heading "Risk Factors" in our most recent Annual Report on Form 20-F and in our Form F-3, as amended, as were filed with the Securities and Exchange Commission and the Israel Securities Authority.Related Semiconductor IP
- Verification IP for C-PHY
- Band-Gap Voltage Reference with dual 2µA Current Source - X-FAB XT018
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
Related News
- Ensphere Leverages TowerJazz's 0.18-micron SiGe BiCMOS Process to Achieve Fully Integrated One Chip Optical Transceiver IC
- TowerJazz Expected to Nearly Double Production Capacity with Proposed Acquisition of Micron Technology Wafer Manufacturing Plant in Japan
- Synopsys and Samsung Collaborate to Deliver Broad IP Portfolio Across All Advanced Samsung Foundry Processes
- Cadence and Samsung Foundry Enter Multi-Year Agreement to Expand Design IP Portfolio
Latest News
- Tord Larsson-Steen appointed new CEO of Shortlink
- GUC Collaborate with Wiwynn to Advance Silicon-to-System Infrastructure for Next-Generation Hyperscale AI
- Two Weebit Nano product customers tape-out; one already demonstrating a functional prototype
- JEDEC Advances DDR5 MRDIMM Ecosystem with New Memory Interface Logic and Expanded MRDIMM Roadmap
- Altera Brings Determinism to Physical AI Systems with Latest Release of FPGA AI Suite