How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
Dolphin Technology
Category:
DDR
SDRAM DDR Controller
Dolphin Technology offers high performance DDR4/3/2 SDRAM and LPDDR5/4x/4/3/2 SDRAM Memory Controller IP across a broad range of …
Overview
Dolphin Technology offers high performance DDR4/3/2 SDRAM and LPDDR5/4x/4/3/2 SDRAM Memory Controller IP across a broad range of process technologies.
These Memory Controllers are fully compliant with the DFI 4.0 specification, support speeds up to 4266 Mpbs, and are optimized to provide a comprehensive solution when combined with Dolphin's DDR PHY IP.
Key features
Compliant with the following specifications:
- Supports JEDEC Standard DDR4/3/2 and LPDDR5/4x/4/3/2 SDRAM
- AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
- AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
- AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
- AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0
DTI SDRAM DDR Controller supports:
- DFI 4.0 Compliant Interface with 1:1 (Matching), 1:2 and 1:4 Frequency Ratios
- Supports speeds of up to 4266 Mbps (2133 MHz) LPDDR4
- Optimized to provide a complete solution along with the Dolphin Technology DDR PHY solution
- Built-in Gate Training, Read/Write Leveling, and VREF Training
- Multi-Port Configurable AXI4 Interface with QoS Signaling
- Single AXI4-Lite Programming Interface
- Multi-port arbitration engine with programmable dynamic priority algorithm ensure high performance and low-latency.
- Pipeline Option for Frequency versus Latency Tradeoff
- Fully configurable for various performances and requirements, ensuring maximum performance for different system environments.
- FPGA portable. Compatible with Xilinx PHY and Altera PHY.
- Available with BFM verification suite.
- Support for AXI4 Dynamic QoS Signaling for Non-Blocking Communications
- Support for Low-Latency Bypass Ports/Channels
- Advanced Dynamic QoS Support Based on the Queuing Theory and Traffic Hysteresis
- Forward Priority Propagation for Queued Transactions
- Traffic-Configurable Address Mapping Scheme with Two Column Segments
- Run-time Configurable Timing Parameters and Memory Settings
- Intelligent Bank Management and Auto-Precharge Scheduling
- Intelligent Traffic Direction Aggregation and Switching
- Programmable and Dynamic Auto-refresh Scheduling
- Proprietary Non-Blocking Priority-Based DDRx/LPDDRx SDRAM Control and Data Buses Access Algorithm
- Real-Time QoS Capability
- Multi-Channel Configuration (Up to 4)
- Multi-Rank Configuration (Up to 4)
- Support for Out-of-Order Memory Access
Specifications
Identity
Part Number
SDRAM DDR Controller
Vendor
Dolphin Technology
Type
Silicon IP
Controller / PHY
Controller
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about DDR IP core
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Frequently asked questions about DDR Interface IP
What is SDRAM DDR Controller?
SDRAM DDR Controller is a DDR IP core from Dolphin Technology listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.