EDA Start-Up Intento Design Raises 900k Euros in Early Stage Funding
Paris, France – November 3, 2015 – Intento Design today announced that it has raised 900k Euros in early stage funding. The equity allows Intento to focus on product development as well as expansion of the company’s global sales and marketing efforts. Key investors in this round of funding include Seventure Partners, a leading European Venture Capital Fund Manager, and the FOREIS Endowment Fund.
Intento Design was founded in spring 2015 to provide responsive technology for analog IP. The company offers an innovative design methodology and tools that accelerate the design and technology migration of analog and mixed-signal integrated circuits. By adding a level of automation to the analog design process, the Intento Design methodology frees design teams to focus on innovation while getting complex SoCs to market faster.
The improved analog design methodology enabled by Intento’s technology provides a critical time-saving solution for designers of connected devices targeting the consumer electronics, Internet of Things (IoT), Big Data, Military, and Medical markets.
About Intento Design
Intento Design provides EDA tools that accelerate the design and technology migration of analog and mixed-signal circuits. By adding a level of automation to the analog design process, the Intento Design methodology frees design teams to focus on SoC innovation while achieving compressed time to market windows. For more information contact: http://www.intento-design.com.
Related Semiconductor IP
- UALink 200G v1.0 Verification IP
- CCSDS SCCC Demapper and Turbo Decoder
- NPU IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
Related News
- ChipAgents Expands Series A Funding to $134 Million as Demand Grows for Agentic AI in Semiconductor Design
- Arteris Wins Funding to Expand Hardware Design Supply Chain Security Assurance for the Trusted and Assured Microelectronics Program
- Intento Enters EDA Market with Software that Accelerates Analog and Mixed-Signal Design, Enables IP Re-Use Through Technology Migration
- CSEM selects ID-Xplore to accelerate analog design and technology porting at functional level
Latest News
- Marvell, Microsoft and Oracle Establish OCP Working Group to Standardize Data Center Hardware Security
- At GAITA, PUFsecurity Shows How PUFrt and PUF-Based HSMs Give Agentic and Physical AI a Verifiable Root of Trust
- QuickLogic Secures Six-Figure eFPGA IP Contract for Automotive Industrial SoC
- Faraday Powers Intelligent Sensing with New 14nm MIPI C/D Combo PHY IP
- Cadence Wins Five 2026 TSMC OIP Partner of the Year Awards