Feroceon processor reorganizes ARM's pipeline, says In-Stat

Marvell has begun sampling its Feroceon chip in an evaluation board, In-Stat said in a newsletter, adding that the 0.15-micron Orion chip is Marvell's first SoC instantiation of Feroceon. Marvell plans to ship parts at clock frequencies of up to 600MHz and parts are sampling, In-Stat added.

The Feroceon makes some significant changes to the standard ARM fixed pipeline, with a variable-stage pipeline that ranges from six stages to eight if the writeback stage is included.

Most ARM processors (and many other embedded processors) employ an in-order, fixed-stage pipeline design because it is simpler to construct and uses less logic, In-Stat said. The instructions per cycle (IPC) of an in-order, fixed-stage pipeline will often be fairly low unless other features are added, such as multithreading or superscalarity.

In contrast, a variable-stage pipeline optimizes the number of clock cycles needed from issue to retire on each instruction, avoids wasting processor resources, and minimizes the branch penalty from dead clock cycles. With these changes to the ARM core, the Feroceon processor could also support dual-issue operation, In-Stat said.