Verification Panel: Are We Done Yet? Not Even Close
When you attend conference panels, you often get everyone agreeing with each other and little real discussion about the deeper issues. But when you sit the same people down in a room together without an audience, those same discussions can become livelier.
That was the case when I got together with Gary Smith, chief analyst at Gary Smith EDA; Paul Martin, senior manager responsible for debug, trace, and performance modeling at ARM; Rajeev Ranjan, chief technology officer at Jasper Design Automation; Harry Foster, chief verification scientist at Mentor Graphics; and Varesh Paruthi, senior technical staff member at IBM.
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