CEO Forecast Panel
This year's CEO forecast panel was held at Silicon Valley Bank. Bankers live better than verification engineers, as if you didn't know, based on the quality of the wine they were serving compared to DVCon.
This year the panelists were Ed Cheng from Gradient, Lip-Bu, Aart and Wally (and if you don't know who they are you haven't been paying attention) and Simon Segars of ARM (not their CEO, of course). Ed Sperling moderated.
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