Vendor: Cadence Design Systems, Inc. Category: PCI Express

Simulation VIP for PIPE PHY

The Cadence® PIPE PHY Verification IP (VIP) provides a mature, capable verification solution for the PHY layer of complex protoco…

Verification IP View all specifications

Overview

The Cadence® PIPE PHY Verification IP (VIP) provides a mature, highly capable verification solution for the PHY layer of complex protocols such as PCIe 3/4/5, USB-3.x, USB-4, DisplayPort and SATA at the Intel PIPE (PHY Interface for PCI Express*, SAA, USB-3, DisplayPort, and Converged IO Architectures). The VIP supports simulation platform and enables metric-driven verification of IP and System on Chip (SoC) designs against PIPE PHY protocol specifications. PIPE PHY VIP is compatible with the industry-standard Universal Verification Methodology (UVM) and supports all leading simulators.

Supported Specifications: Intel PIPE version 4.3, 4.4,1 and 5.2 specifications.

Key features

  • Device Type
    • PipeXceiver
    • SerialXceiver
    • PHYDUT Monitor
    • PHY Active VIP
  • PHY Architecture
    • Original PIPE architecture
    • SerDes Architecture
  • Pin Interface
    • Legacy Pin Interface
    • Low Pin Count Interface
  • Protocols Mode
    • USB 3.x
    • PCIe 3/4/5
    • USB4
  • Data Transmission Rate
    • USB 3.x: 5GT/s, 10GT/s
    • USB4: 10 GT/s. 20 GT/s, 10.3125 GT/s, 20.625 GT/s
    • PCIe: 2.5 GT/s, 5.0 GT/s, 8.0 GT/s, 16.0 GT/s,32.0 GT/s
  • Clock Support
    • External Bit Clock
    • Internal Bit Clock (Recovery from Serial bit stream)
  • PCLK Modes
    • PCLK as PHY Input
    • PCLK as PHY Output
    • PCLK as both
  • LFPS
    • Supported
  • PIPE Data Width
    • 8/10, 16/20, 32/40 and 64/80 bit
  • Message Bus
    • M2P and P2M Transactions supported
    • All Message bus commands supported
    • Write Uncommitted
    • Write Committed
    • Read
    • Read Completion
    • Write ACK
  • Integrated Mode with Protocol VIP
    • USB3 , USB4, including Pipe
    • Phy Integrated Mode, is supported

Block Diagram

Simulation VIP for PIPE PHY block diagram

Specifications

Identity

Part Number
Simulation VIP for PIPE PHY
Vendor
Cadence Design Systems, Inc.
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about PCI Express IP core

PCI Express Security and TEE Integration, Part 1 - Establishing Trust

Protecting processor memory alone is no longer sufficient. The entire I/O path must become part of the trusted computing architecture. To address this challenge, PCI-SIG® has developed a suite of complementary security technologies, including Data Object Exchange (DOE), Component Measurement and Authentication (CMA), Integrity and Data Encryption (IDE), and the TEE Device Interface Security Protocol (TDISP).

How a Multi-Protocol PHY Simplifies Physical AI Connectivity

Physical AI systems must move large amounts of data across two very different connectivity domains. Accelerators and local storage need high-bandwidth, low-latency links close to the compute SoC, while sensors and control modules require reliable connectivity across the larger platform. Supporting both domains with separate high-speed PHYs can increase silicon area and integration complexity.

Frequently asked questions about PCIe IP cores

What is Simulation VIP for PIPE PHY?

Simulation VIP for PIPE PHY is a PCI Express IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this PCI Express?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PCI Express IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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