The Increasing Role of SystemC in System Design
Today's post is less technical and a bit more theoretical, but I promise that my next post will be more hands-on.
As somebody working on virtual platforms in an EDA company, I regularly spend time talking to firmware and embedded software engineers with many different backgrounds. Every so often one of them asks, "Why SystemC?" Some software engineers look at SystemC and decide that it looks like a real mess. They mention things like:
- SystemC has complex classes built with C++
- It uses strange macros like SC_MODULE, SC_METHOD, and SC_HAS_PROCESS
- Sometimes it can be difficult to find the cause of compilation errors
- SystemC takes a long time to compile
- Generally it doesn't provide much benefit for all this complexity
They ask, "what is wrong with plain C++ or even plain old C?" Most of the time they ask these questions because they don't understand how everything fits together.
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