The Semiconductor Landscape In A Few Years?
Looking at the huge gap between the revenue of semiconductor design and manufacturing (~$300B) and that of EDA tools, services and silicon IP combined (~6B) inspired me to look more deeply into the overall arena of semiconductors in today’s context and possibly decipher some trends which should emerge in near future. Although this gap in revenue always existed, in the realm of SoCs and ever increasing complexity on a single wafer over last few years, the gap seems to be justified and may open up new chapters in the semiconductor arena. I have been watching the developments in this space for a few years and the industry seems to be at an inflexion point. This prompted me to write this article.
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