Want a peek at a possible Qualcomm 3D IC roadmap?
April 11, 2012
“3D IC test wafers will run this year and high-volume 3D IC manufacturing will start in 2013,” concluded Riko Radojcic at the end of his EDPS keynote on 3D ICs held in Monterey, California last Friday. Radojcic is Qualcomm’s Director of Engineering, so he just might know something about the state of 3D IC assembly although he’s not necessarily referring to Qualcomm in the above statement. His concluding remarks came at the end of an hour’s worth of hard-earned 3D IC assembly and design insights that Radojcic has assembled at Qualcomm.
To read the full article, click here
Related Semiconductor IP
Related Blogs
- Semicon West: The Roadmap is 3D IC
- Qualcomm, AMD head top 25 fabless IC suppliers for 2009; Taiwan firms finish strong!
- What's driving 3D IC design? Do 2D EDA tools need a total overhaul to support 3D design?
- Qualcomm: Scaling down is not cost-economic anymore - so we are looking at true monolithic 3D
Latest Blogs
- Pioneering Secure-by-Design in the Age of the European CRA
- Overcoming power management IP challenges
- Running OpenCode with llama.cpp and Qwen 3.5 on E-Series
- Automated, Faster Specification to Sign-Off with IDS-AI
- NovaTech Automation Crius PIU: Bringing Conventional Instrument Transformers onto the IEC 61850 Process Bus