Formally verifying protocols
November 16, 2011
I attended much of the Jasper users' group a week ago. There were several interesting presentations that I can't just blog about because companies are shy, and some that would only be of interest if you were a user of Jasper's products on a daily basis.
But for me the most interesting presentations were several on an area that I didn't realize this sort of formal verification was being used for. The big driver is that modern multi-core processors now require much more sophisticated cache control than before. ARM in particular has created some quite sophisticated protocols under the AMBA4 umbrella that they announced at DAC.
To read the full article, click here
Related Semiconductor IP
- Mesochronous Bridge for PCIe/CXL
- AI-native GPU
- OpenGMSL Verification IP
- OpenGMSL Leaf IP
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
Related Blogs
- Addressing Heterogenous Verification and Validation Requirements for Compute Express Link (CXL) Designs Using Synopsys Protocol Continuum
- Standing the Test of Time: How Advanced Protocol Verification Creates Bulletproof SoC Designs
- How to Speed Up Simulation Coverage Closure with Formal Verification Tools
- Raising RISC-V processor quality with formal verification
Latest Blogs
- Automated, Faster Specification to Sign-Off with IDS-AI
- NovaTech Automation Crius PIU: Bringing Conventional Instrument Transformers onto the IEC 61850 Process Bus
- Single Pair Ethernet and TSN: The In-Robot Network Behind the Next Humanoid Robots
- A design path to success exists for ultra-low-voltage SoCs
- Where Routine Flow Ends Veriest Formal Expertise Begins