Raising RISC-V processor quality with formal verification
During the development of a mid-range complexity RISC-V processor, you can discover hundreds or even thousands of bugs. As you introduce more advanced features, you inadvertently introduce new bugs that vary in complexity. Certain types of bugs are just too complex for simulation to find them. You must therefore augment your RTL verification methods. How do you do that? By adding formal verification. From corner cases to hidden bugs, it allows you to exhaustively explore all states within a reasonable amount of processing time. Let’s have a look in this blog post at how we can raise the quality of RISC-V processors with formal verification.
Why use formal verification for RISC-V?
RISC-V is a modular instruction set architecture for which an architectural test suite can be developed. It is used in simulation-based verification to verify a processor implementation. Similarly, formal methods can be used to verify the architectural compliance of a processor. Why? Because RISC-V is an open standard that everyone can use as a reference model to formally verify an implementation.
To read the full article, click here
Related Semiconductor IP
- RISC-V Debug & Trace IP
- RISC-V IOPMP IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- 64-bit RISC-V core with in-order single issue pipeline. Tiny Linux-capable processor for IoT applications.
- Multi-core capable RISC-V processor with vector extensions
Related Blogs
- Improving RISC-V Processor Quality with Verification Standards and Advanced Methodologies
- Accelerating RISC-V Processor Verification: A Co-Simulation Strategy
- Why Codasip Cares About Processor Verification - and Why you Should too
- Building a Swiss cheese model approach for processor verification
Latest Blogs
- Tape-Out Readiness Checklist: Engineering Decisions That Prevent Costly Respins
- How Cadence DSPs Put In-Cabin AI Audio On-Chip in SemiDrive's X10
- The Fastest Path to Scalable Photonic Systems: Using Proven IP for both PIC and EIC designs
- Building Trusted AI Agents from the Silicon Root of Trust
- Heterogeneous Computing in Space