Processor architecture optimization is not a barrier for university researchers

By Codasip

May 3, 2022

With closed processor Instruction Set Architectures (ISA) with limited access to processor Intellectual Property (Arm and x86), university professors have often limited their research to two main spheres: optimizing software algorithm(s) and external hardware. University researchers have not been able to consider optimizing the processor due to the lack of access to processor Intellectual Property (IP). Where these two spheres overlap, trade-offs are made to optimize the solution. A conventional research barrier is the exclusion of processor architecture optimization. Coprocessors or external accelerators can be explored, but they are limited and costly in solving tomorrow’s technological challenges in Processor Security, Functional Safety, Intelligent Memories, and Artificial Intelligence.

We launched the Codasip University Program in March 2022 to support you, engineering professors and students, and advance technology that will solve tomorrow’s technological challenges. Because of Moore’s Law and Dennard’s Scaling challenges, computer architects have developed solutions through integrating multiple homogenous and heterogenous cores. Tightly coupling application acceleration and application-specific requirements into the processor core is a new research domain to solve tomorrow’s computational needs. Let see, in this blog post, how you can jump start on this opportunity with our program.

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