PCIe 5.0 Controller IP on FPGAs: Current and Future Use Cases
Rambus announced this week that it demonstrated for the first time a PCI Express 5.0 Controller IP (PCIe 5 Controller) operating at 32 GT/s on a leading FPGA platform.
“We’ve achieved a new industry benchmark with the demonstration of our PCIe 5.0 Controller operating at 32 GT/s on popular FPGA platforms,” said Scott Houghton, general manager of Interface IP at Rambus. “With the importance of FPGAs in markets from defense to the data center, this solution developed by the newly-acquired PLDA team expands the Rambus portfolio and offers the next level of performance for mission-critical applications.”
Beyond the technical feat, you might wonder: what are the benefits for Rambus customers?
To read the full article, click here
Related Semiconductor IP
- PCIe 5.0 Controller
- PCIe 5.0 Controller with AXI
- CXL 2.0 Controller with AXI
- CXL 2.0 Controller
- PCIe 5.0 (Gen5) Standard Controller with AMBA bridge II
Related Blogs
- Rambus Achieves PCI Express® (PCIe®) 5.0 Compliance for PCIe 5.0 Controller IP and Inspector PCIe 5.0 Interposer with Diagnostic IP
- FiRa 3.0 Use Cases: Expanding the Future of UWB Technology
- Tech Note: Use this Flexible and Efficient AC’97 IP Core for Simple Audio Interfaces and Legacy System Upgrades
- Synopsys Delivers First Complete UFS 5.0 and M‑PHY v6.0 IP Solution for Next‑Gen Storage
Latest Blogs
- Beyond Trusted: What the NSA’s New Guidance Means for Hardware Security
- A scalable, shader-programmable vector graphics GPU core for low-power MCUs
- Navigating ISO 26262 Part 11: A Guide for Semiconductor Architects
- Embedded Security explained: Digital signatures
- Hardware security verification must go beyond functional testing