PCIe 5.0 Controller IP on FPGAs: Current and Future Use Cases
Rambus announced this week that it demonstrated for the first time a PCI Express 5.0 Controller IP (PCIe 5 Controller) operating at 32 GT/s on a leading FPGA platform.
“We’ve achieved a new industry benchmark with the demonstration of our PCIe 5.0 Controller operating at 32 GT/s on popular FPGA platforms,” said Scott Houghton, general manager of Interface IP at Rambus. “With the importance of FPGAs in markets from defense to the data center, this solution developed by the newly-acquired PLDA team expands the Rambus portfolio and offers the next level of performance for mission-critical applications.”
Beyond the technical feat, you might wonder: what are the benefits for Rambus customers?
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