Find Everything You Need to Build an Advanced PCI Express 4.0 Solution in One Booth - Visit Cadence at PCI-SIG DevCon 2015
The PCI-SIG Developers Conference happening today and tomorrow will be yet another exciting PCI-SIG event that Cadence is proud to participate in. We’ve been attending and showcasing technology at these conferences for many years now, sharing news and insights about our verification IP, controllers, and PHY solutions.
Cadence was the first commercial PCI Express 3.0 IP provider, and has continued that tradition by engaging with key server customers for PCI Express 4.0. The latest incarnation of the specification doubles the maximum bandwidth for a 16-lane configuration to a whopping 256 GTps.
This protocol revision is driven by the need for more data to be transported faster across the interface. Technology adoption in the consumer space is a key factor: the amount of data transferred across the Internet by the end of 2016 is estimated to be a zettabyte (1 followed by 21 zeroes!), according to a Cisco report. Video comprises a significant portion of this traffic. The same Cisco report states that every second, nearly a million minutes of video content will cross the network by 2019.
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Related Semiconductor IP
- PCI Express 4.0 PHY
- Configurable PCI Express 4.0 Link Controller
- PCIe 4.0 PHY in TSMC(6nm,7nm, 12nm,16nm)
- Multi-Port Switch IP for PCI Express
- PCIe PHY and controller solution
Related Blogs
- PCI Express Trends and News at PCI-SIG 2016
- CCIX Protocol Push PCI Express 4.0 up to 25G
- PCI Express: Delivering Needed Bandwidth for Open Compute Project
- Doubling Bandwidth in Under Two Years: PCI Express Base Specification Revision 5.0, Version 0.9 is Now Available to Members
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