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Vendor:
Synopsys, Inc.
Category:
Single-Protocol PHY
Multi-Port Switch IP for PCI Express
The IP for PCI Express with Single Root I/O Virtualization (SR-IOV) implements a configurable and scalable SR-IOV solution provid…
Overview
The IP for PCI Express with Single Root I/O Virtualization (SR-IOV) implements a configurable and scalable SR-IOV solution providing designers with a high-quality IP that reduces risk and improves time-to-market. The silicon-proven SR-IOV IP is compliant to the latest PCI Express, PIPE and SR-IOV specifications and has been extensively validated with multiple hardware platforms, PHYs and PCIe verification suites. As the industry standard for PCI Express,the vendor offers a comprehensive IP solution that is in volume production and has been successfully implemented in a wide range of applications.
The synthesizable core integrates quickly and easily into SoC designs with a user-friendly application interface and conservative timing suitable for a wide range of ASIC and FPGA technologies. The core is available in your choice of datapath widths, PIPE interface widths, and operating frequencies for optimization of size, power, and throughput. The vendor's PCI Express cores are fully compliant with the PCI Express Base Specifications and are used to power the industry's PCI Express compliance testing at PCI-SIG Compliance Workshops.
Key features
- Designed according to the PCI Express 4.0, 3.1, 2.1, and 1.1 specifications, including the latest errata
- Designed according to the PCI-SIG Single-Root I/O Virtualization specification
- Supports PIPE PHY interface definition including variable clock and variable data
- Supports 16.0, 8.0, 5.0 and 2.5 Gbps line rates
- Architecture supports x1, x2, x4, x8, and x16 lanes
- Available in 32-, 64-, 128-, 256- and 512-bit data path widths for maximum flexibility
- Support for up to 32 Physical Functions (PFs)
- Support for up to 256 Virtual Functions (VFs), which are dynamically allocated
- Interface for support of the Address Translation Specification
- Alternative Routing ID Interpretation (ARI)
- Function Level Reset (FLR)
- Advanced Error Reporting (AER) supported per VF
- Power Management (PM) per VF supported
- Optimal on-chip memory utilization and low latency
- Legacy PCI, MSI and MSI-X interrupt support
- Multi-function support
- ASIC and FPGA support
Block Diagram
dwc_pci_express_multi-port_sw block diagram
Specifications
Identity
Part Number
dwc_pci_express_multi-port_sw
Vendor
Synopsys, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about Single-Protocol PHY IP
What is Multi-Port Switch IP for PCI Express?
Multi-Port Switch IP for PCI Express is a Single-Protocol PHY IP core from Synopsys, Inc. listed on Semi IP Hub.
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.