Memory Model Tool: Morello (and some Memory Tagging)
This post presents the implementation of Morello in the Memory Model Tool. The reader is expected to have some understanding of the tool, which is documented in previous posts: A working example of how to use the herd7 Memory Model Tool and How to generate litmus tests automatically with the diy7 tool.
Morello
Morello is a security architecture developed by Arm, based on Capability Hardware Enhanced RISC Instructions (CHERI). More information can be found in the Arm Morello program.
We have extended the Memory Model Tools to support Morello:
https://github.com/herd/herdtools7/commit/ef79f222ed8ad77c79457c3c9c77a945f12bf9fb
Extending the Memory Model Tools to include the Morello instruction set increases the coverage of the tools. This benefits hardware developers and software developers during the prototyping of Morello evaluation boards and the code that runs on them. There are several aspects that are of interest in the implementation of Morello in the Memory Model Tool, namely the addition of:
- New instructions or new variations of instructions specific to Morello
- New types of memory accesses
- Interaction between Morello and other instructions
To read the full article, click here
Related Semiconductor IP
- NPU IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
- NVMe Validation Test Suite
- Hybrid Memory Cube Verification IP
Related Blogs
- Buying DDRn Controller IP AND Memory Model to the same IP vendor gives real TTM advantage
- The RISC-V Memory Consistency Model
- How to Reduce Memory Model Debug Time
- LPDDR6: A New Standard and Memory Choice for AI Data Center Applications
Latest Blogs
- Tape-Out Readiness Checklist: Engineering Decisions That Prevent Costly Respins
- How Cadence DSPs Put In-Cabin AI Audio On-Chip in SemiDrive's X10
- The Fastest Path to Scalable Photonic Systems: Using Proven IP for both PIC and EIC designs
- Building Trusted AI Agents from the Silicon Root of Trust
- Heterogeneous Computing in Space