The RISC-V Memory Consistency Model
April 24, 2017
Memory consistency models (MCMs) are known to flummox even experienced computer architects, so it is perhaps not surprising that recent news articles had some difficulty portraying the nuances behind recent findings by a team of Princeton researchers led by Professor Margaret Martonosi. The RISC-V Foundation is publishing this article to help the RISC-V community understand the deeper implications of the Princeton study.
To read the full article, click here
Related Semiconductor IP
- 64-bit, RISC-V, ultra-high performance processors
- 64-bit, RISC-V, performance and data computation processors
- 32-bit, RISC-V, deeply embedded processors
- RISC-V Display Connectivity Subsystem (DCS)
- RISC-V IOPMP IP
Related Blogs
- Buying DDRn Controller IP AND Memory Model to the same IP vendor gives real TTM advantage
- How to Reduce Memory Model Debug Time
- Memory Model Tool: Morello (and some Memory Tagging)
- RISC-V for Infrastructure: For Now, It’s All About the Developer
Latest Blogs
- CDM Dependence on Device Capacitance
- What the Cyber Resilience Act means for the future of chip design
- When Your IP Vendor Has Operated 150,000 Base Stations: Introducing Viettel Semiconductor
- Relationship between architecture and validation in system design
- The Post-Quantum Cryptography Mandate: Building Cryptographically Agile Systems for the Quantum Era