Life After 28nm: Think Network-on-Chip

By EETimes

July 28, 2014

As Moore's Law reverses and 20, 16, and 14 nanometer processes become more expensive, SoC cost reductions must come from design innovations within more mature processes and established methodologies.

The days are over when companies can expect to make a profit by introducing a so-so product at first but count on a second, higher-performing release manufactured using a smaller process.

Every design team knows the value of quality improvements in the following areas:

• Smaller die size
• Higher bandwidth
• Lower power
• Greater productivity
• Flexible quality of service

However, SoC design realities in the present era make it imperative to closely reevaluate mature semiconductor processes to realize greater efficiencies that yield lower costs, higher performance, and shorter time to market.

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