Increased CHI Coherency Verification Challenges

By _Cadence - Cadence IP Blog

February 13, 2015

Cache coherency is not unique to the new ARM® AMBA® 5 CHI (Coherent Hub Interface) specification that enables processors to work together in high-performance, coherent processing “hubs”, and to deliver the high data rates that are common in enterprise markets, such as servers and networking. Coherent architectures have existed for many generations of CPU designs, but verifying adherence to coherency rules has always been one of the most complex challenges faced by verification engineers. However, it becomes even more challenging with increasing number of cores and the introduction of the embedded L3 (level 3) cache to the interconnect device, both of which are hallmarks of CHI-based SoCs.

The fundamental challenge of coherency is that when data is requested by a core (a "master" in the language of coherency), it is not known where the data will be found. The data may return from various sources: system memory, the interconnect's L3 cache, or one of the caches associated with the other masters in the SoC.

To gain an appreciation for this, let's look at an example of a few read commands to the same address in a multi-core system, as shown in the figure below.

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