CCIX Coherency: Verification Challenges and Approaches

By Cadence

January 25, 2018

Cache coherency is not a new concept. Coherent architectures have existed for many generations of CPU and Interconnect designs. Verifying adherence to coherency rules in SoCs has always been one of the most complex challenges faced by verification engineers. Over the years, it became even more challenging with increasing number of cores in CPU clusters and introduction of the embedded L3 (level 3) cache to the coherent interconnect devices. Advent of inter-chip coherency with the new CCIX (pronounced see-six) protocol elevates this challenge to a whole new level. The basic idea behind CCIX, is to define a single coherent infrastructure for multiple SoCs such CPUs, GPUs, and Accelerators.

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