How to Shift Left on Low-Power Design Verification, Early and Quickly

By Synopsys, Inc.

May 9, 2023

As the semiconductor industry moves toward smaller process nodes, static power has become a primary design constraint. This has necessitated development of various power management techniques. For example, designers might create multiple voltage domains or use isolation cells to isolate a shut-down power domain from a powered-on domain. They might apply a level shifter to scale signal voltages up or down as they propagate from one domain to another, or use retention cells for faster return of a register to its state before shut down. Like a hardware description language (HDL) to specify functional intent of a design, implementing these techniques requires a common language to specify the design’s power intent: Unified Power Format (UPF).

Considering how highly complex and often specific to an application today’s SoCs are, the effort that goes into designing and achieving desired functionality along with timing and power requirements is enormous. But merely meeting these goals is not enough. The end user’s insatiable desire for the latest features in the shortest amount of time creates pressure on the IP development team. In order to meet time-to-market goals, chip design companies often adopt a parallel development approach where different teams write register-transfer level (RTL), Synopsys Design Constraints (SDC) files, UPF files, and so on.

Even though the development of the design and UPF go hand in hand, their schedules might vary, which can lead to some challenges. In this blog post, I’ll explain how you can overcome these challenges with Synopsys VC LP™ Design-Independent UPF Checker (VC UPF). Read on to learn how VC UPF lets you clean up design-independent issues in the UPF file even before RTL is ready.

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