How to Model and Simulate 112Gbps PAM4 SerDes Using IBIS-AMI
May 27, 2019
With the buildout of 5G wireless networks and the constant demand for bandwidth in cloud-based data centers, serial link data rates continue to skyrocket. The current state-of-the-art serial links use 112Gbps data rates, using PAM4 signaling. PAM4 differs from traditional NRZ signaling in that it transmits 2 bits per symbol, effectively reducing the need for bandwidth by half.
To enter this hot and competitive market, Cadence purchased a startup company in late 2017 called “nusemi Inc.”, and immediately began work on a 112Gbps PAM4 SerDes IP offering.
To read the full article, click here
Related Semiconductor IP
- 1-112Gbps Serdes - 7nm
- HDMI 2.1 TX PHY 12Gbps in TSMC N5 1.8V, North/South Poly Orientation
- HDMI 2.1 RX PHY 12Gbps in TSMC 16FFC 1.8V, North/South Poly Orientation
- HDMI 2.1 RX PHY 12Gbps in TSMC 12FFC 1.8V, North/South Poly Orientation
- HDMI 2.1 Rx PHY 12Gbps in SS 14LPP, North/South Poly Orientation
Related Blogs
- How to Solve the Size, Weight, Power and Cooling Challenge in Radar & Radio Frequency Modulation Classification
- The 5 Biggest Challenges in Modern SoC Design (And How to Solve Them)
- Why 6.4 Gbps DDR5 Designs Fail and How to Avoid It
- Using SystemC TLM Modeling To Solve AI Data Movement Challenges
Latest Blogs
- Would custom memory ease your SoC design?
- Embedded Security explained: Advanced Encryption Standard (AES)
- Cadence Demonstrates PCIe 8.0 PHY at PCI-SIG DevCon 2026
- Cadence Achieves Successful Silicon Validation of 1st IP Test Chips on Intel 18A
- From Classical CAN and CAN FD to CAN XL: Functional Safety and Security for Next-Generation In-Vehicle Communication