How to Model and Simulate 112Gbps PAM4 SerDes Using IBIS-AMI
May 27, 2019
With the buildout of 5G wireless networks and the constant demand for bandwidth in cloud-based data centers, serial link data rates continue to skyrocket. The current state-of-the-art serial links use 112Gbps data rates, using PAM4 signaling. PAM4 differs from traditional NRZ signaling in that it transmits 2 bits per symbol, effectively reducing the need for bandwidth by half.
To enter this hot and competitive market, Cadence purchased a startup company in late 2017 called “nusemi Inc.”, and immediately began work on a 112Gbps PAM4 SerDes IP offering.
To read the full article, click here
Related Semiconductor IP
- Complete 1.6T Ultra Ethernet IP Solution
- 100G SerDes PAM4 PHY
- Die-to-Die, High Bandwidth Interconnect PHY in TSMC (N7, N5)
- 112G Ethernet PHY in TSMC (N7, N5, N3P)
Related Blogs
- How to Solve the Size, Weight, Power and Cooling Challenge in Radar & Radio Frequency Modulation Classification
- The 5 Biggest Challenges in Modern SoC Design (And How to Solve Them)
- Why 6.4 Gbps DDR5 Designs Fail and How to Avoid It
- Using SystemC TLM Modeling To Solve AI Data Movement Challenges
Latest Blogs
- M31 High-Speed and Long-Channel MIPI C/D-PHY Solution on TSMC N3P/N3C
- Understanding security certification and how analog IP can help
- Embedded Security explained: Secure boot for embedded systems
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects
- One Key for Every Door: How Aliro Extends the UWB Digital Key Beyond the Car