How PCIe 7.0 is Boosting Bandwidth for AI Chips

By Synopsys, Inc.

June 10, 2024

While headlines about the rapidly evolving nature of artificial intelligence (AI) continue to abound, the need for advanced and efficient hardware infrastructure is becoming more critical than ever before. Large language models (LLMs) continue to grow in complexity and double the number of parameters required every four to six months. In fact, GPT-4 has more than one trillion parameters! While this statistic is simple, the sheer amount of data this translates to is mind-boggling (2 trillion bytes or 200,000 high-resolution photos/500,000 documents). Moving these vast data sets requires robust, high-bandwidth interconnects to transfer all this information as fast and reliably as possible.

Complex LLM algorithms and powerful accelerators/processors mean nothing if the data gets stuck in traffic bottlenecks. Current hyperscale data center infrastructures can’t keep up with the speed and low latency needed to process and store these models at scale. To change the game, hyperscalers and the entire supporting ecosystem need to consider transforming down to the silicon level to enable the scaling of systems that can handle petabyte-level data in real time while improving power efficiency.

That’s where PCIe 7.0 comes into the picture, the latest iteration of the PCI Express standard. PCIe 7.0 offers up to 512 GB/s of bandwidth and ultra-low latency, and is poised to handle the massive parallel computing needs of AI workloads to help mitigate data bottlenecks. Today, Synopsys is launching the world's first complete PCIe 7.0 IP solution to enable secure data transfers and boost bandwidth for the next generation of AI and HPC chips.

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