Efficiency Defines The Future Of Data Movement

By Andy Nightingale

October 31, 2025

For decades, chip performance was measured by how much raw compute could be packed onto a die. However, that equation has changed. Moving data across a system-on-chip (SoC) now consumes more energy than the computations it performs. Efficient data movement has become a significant challenge for next-generation SoC designs. AI workloads are multiplying, hyperscale data centers are approaching power limits, and chiplet adoption is reshaping integration strategies.

This is especially evident in the data-hungry demands of AI. Generative models involve moving billions, sometimes trillions, of model parameters between high-bandwidth memory (HBM) and processing elements. Every byte that moves consumes energy, and the cumulative effect is staggering. Without significant efficiency gains, the power required for advanced AI systems could multiply several times over current levels, straining global energy resources. This reality reframes performance. It is no longer about achieving more speed at any cost but about operating within finite power budgets.

Lessons from mobile power management

Demand for efficiency isn’t new. In the early days of mobile phones, engineers faced severe power and thermal limits yet needed to maintain instant responsiveness. Arteris played a pioneering role in this era. The company’s network-on-chip (NoC) technology enabled early smartphone SoC developers to balance performance and efficiency across on-chip communication and power domains. These advances proved that intelligent data movement could deliver both performance and endurance within tight energy constraints.

Those same principles now apply to AI-driven designs, where energy efficiency is a key factor in scalability. Modern workloads require continuous data exchange among tightly integrated compute arrays, creating power data movement bottlenecks and escalating power density far beyond that of mobile devices. Techniques first proven in mobile SoCs, such as subsystem shutdown, clock gating, and fast wake-up, provide a proven foundation for managing these challenges. The ability to dynamically isolate and reactivate NoC regions allows teams to control power and thermal behavior while maintaining predictable latency and throughput.

To read the full article on Semiconductor Engineering, click here.