IP Roundtable, Part 5: Is EDA Unfair Competition?
At the end of the previous segment of this experts' roundtable, we were talking about the number of IP companies being bought by EDA companies. We continue to explore the relationship between IP developers and EDA companies here. Taking part in today's discussion are Warren Savage, CEO of IPextreme; John Koeter, vice president of marketing for the solutions group at Synopsys; and Chris Rowen, Cadence Fellow and CTO at Tensilica.
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