DDR5 IP Test Chip Operates with Micron Prototype DRAM at 4400 MT/s
The DDR5 standard has not been finalized by JEDEC, and they are very strict about not allowing anyone to claim DDR5 compatibility until the standard is complete. That is expected sometime this summer. However, getting designs into silicon can't wait until the standard is final before getting started. In principle, anything could change in the standard at any time until it is released, but everyone knows that the basic parameters are not going to change at this late date. Almost exactly two years ago, Mellanox's Gilad Shainer said to me that "interoperability is the only way to prove standards compliance." He was talking about PCIe 4.0, a standard that hadn't been completed when we talked. But the same idea applies to next-generation DRAM.
To read the full article, click here
Related Semiconductor IP
- DDR5 & DDR4 COMBO IO for memory controller PHY, 4800Mbps on TSMC 12nm
- DDR5 MRDIMM PHY and Controller
- MRDIMM DDR5 & DDR5/4 PHY & Controller
- DDR5 Serial Presence Detect (SPD) Hub Interface
- DDR5 Controller - Ensures high-speed, efficient operation and compatibility of memory controllers
Related Blogs
- How We Developed and Tested a Prototype DDR5 Interface in Silicon Based on a Preliminary Version of the DDR5 Standard
- Samsung 20nm test chip includes ARM Cortex-M0 processor core. How many will fit on the head of a pin?
- UMC Test Chip for Cadence Interface IP Is Working
- Synopsys and Intel Team Up on the First UCIe-Connected Chiplet-Based Test Chip
Latest Blogs
- AI in Design Verification: Where It Works and Where It Doesn’t
- PCIe 7.0 fundamentals: Baseline ordering rules
- Ensuring reliability in Advanced IC design
- A Closer Look at proteanTecs Health and Performance Management Solutions Portfolio
- Enabling Memory Choice for Modern AI Systems: Tenstorrent and Rambus Deliver Flexible, Power-Efficient Solutions