Configurable LLDB for (not only) embedded RISC-V processors

By _Codasip Blog

September 12, 2023

At some point, software developers or processor developers need to check and debug their code. They can do this at different levels, for example looking at waves or parsing printouts, but the preference is to check code in an interactive session. The debugger facilitates the interactive session by accepting developers’ commands, executing them, and showing the results. For example, showing a variable value while being stopped at a particular line of the code. In this blog post, let’s focus on the LLDB, a debugger developed under the LLVM project.

Debuggers and customization

Debuggers usually support multiple targets such as x86, Arm, or RISC-V. They have an embedded knowledge of these targets (also known as ABI), such as which registers are visible to a programmer, which instructions the target has, or how the memory map looks like. However, RISC-V brought a new dimension. RISC-V supports and endorses custom extensions, which means that the processor may have more instructions and/or registers that are interesting for developers, yet the standard RISC-V target is not aware of them.

This is something that Codasip solutions handle perfectly. The beauty of it? The solutions scale not only for RISC-V architectures, but for pretty much any architecture described using Codasip Studio tools (that is, custom processors).

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