Simulation VIP for CCIX
Cadence provides a mature and comprehensive Verification IP (VIP) for the CCIX specification which is an open standard for a new …
Overview
Cadence provides a mature and comprehensive Verification IP (VIP) for the CCIX specification which is an open standard for a new class of server products that addresses the challenging performance and latency requirements in the growing data center market. Incorporating the latest protocol updates, the Cadence® Verification IP for CCIX provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Cadence provides a solution for interconnect verification that supports the verification of coherent interconnect. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for CCIX helps you reduce time to test, accelerate verification closure, and ensure end-product quality.
The CCIX VIP showcases Cadence’s pioneering efforts in the enterprise data center market by being the first to announce a VIP-DIP solution. With early customer engagements prior to specification ratification and joint collaboration with Cadence DIP, this VIP allows customers to leverage our expertise in PCIe and cache coherency from the verification and design spectrum.
Built on top of known and proven PCIe and AMBA verification solutions, the CCIX VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).
Supported specification: The Protocol Layer of CCIX 1.0, 1.1, and 2.0 specifications.
Key features
- CCIX Protocol Layer
- Fully models the CCIX Protocol Layer
- CCIX Transport Layer
- Should be used in conjunction with either CXS or PCIe VIP which model the Transport Layer
- TX and RX Channels
- TX and RX channels simultaneously
- Snoop Filter
- Snoop filter functionality and API at HA agent
- Snoop Broadcast
- Supports snoop broadcast
- SA Memory Expansion
- Supports SA memory expansion
- PCIe Header Support
- PCIe Optimized and Standard Headers
- Protocol Credit Control
- Full control over protocol credits
- Dedicated VC
- Dedicated VC for CCIX traffic that can be configured to
- Send/Receive vendor-defined messages with CCIX payload
- Send/Receive CCIX Optimized TLP
- Packet Mode (Legacy)
- Variable packet size used for packing and transmitting messages
- Container Mode
- Packing of messages into 64B containers and passing them to lower layer
- Increased Message Credits for CCIX 2.0
- Increased the number of credits from 2 to 64 for eafurther information.
Block Diagram
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about CCIX IP core
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Frequently asked questions about CCIX IP cores
What is Simulation VIP for CCIX?
Simulation VIP for CCIX is a CCIX IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.
How should engineers evaluate this CCIX?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CCIX IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.