CCIX 1.0 Verification IP

CCIX Verification IP provides an smart way to verify the CCIX bi-directional bus. The SmartDV's CCIX Verification IP is fully compliant with CCIX Base Specification revision 1.0 version 1.0 and provides the following features.

CCIX 1.0 Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

CCIX 1.0 Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Supports CCIX Base Specification revision 1.0 version 1.0
• Support all Write, Read, Data less and Atomic transaction.
• Supports all Request responses and Snoop responses.
• Device and Normal memory types support.
• Support for all Transaction types/Opcodes.
• Supports complaint and optimized TLP packets.
• Supports multiple Coherency messages in one TLP.
• Supports CCIX Extended speed mode
• Supports PIPE, PCS/PMA, and serdes interface.
• UVM and Verilog APIs supplied, as well as C DPI exports.
• Full link speed and width negotiation up to 32 Lanes.
• Automated Error Injections at all layers.
• Checkers verify protocol timing checks and functional accuracy at each layer.
• Queuing for VCs with configurable depth.
• Configurable TC to VC queue mapping.
• User interface for direct TLP queuing and receipt.
• Checks all TLPs for correct formation of headers, prefixes, and ECRC.
• Full DL state machines.
• Checks all framing, LCRC, and lane rules.
• Check all DLLP fields and formatting.
• Interface to send / receive user defined DLLPs.
• Full LTSSM state machine.
• SERDES model with digital clock recovery.
• Supports Up configure, polarity inversion, and lane-to-lane skew.
• Configurable Spread Spectrum Clocking (SSC).
• Configurable timers and timeouts.
• Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
• CCIX Verification IP comes with complete test suite to test every feature of CCIX specification.
• Functional coverage for complete CCIX features.
• Callbacks in BFM's and Monitor for various events.
• Scaled Flow Control.
• Data Link Feature Exchange.
• Lane Margining at Receiver.
• Enhanced Allocation.
• Emergency Power Reduction State.

• Faster testbench development and more complete verification of CCIX designs.
• Easy to use command interface simplifies testbench control and configuration of CCIX TX and RX.
• Simplifies results analysis.
• Runs in every major simulation environment.

• Complete regression suite containing all the CCIX testcases to certify CCIX BFM's.
• Examples showing how to connect various components, and usage of CCIX TXRX BFM and Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.